SIGNAL CONDITIONING LOGIC

SIGNAL CONDITIONING LOGIC An apparatus for conditioning signals output from a computer system expansion card to a computer system board to test system board bus specifications and timing limits. The apparatus comprises two signal conditioning extension cards which are used to condition signals from a slave card and a bus master card. The signal conditioning extension cards according to the present invention are interposed between the bus master or slave expansion card and the system board and selectively advance or delay the signals output from the expansion card to the system board. The slave signal conditioning card also selectively delays the read data valid window of the slave card to test the limits of the system board. The bus master signal conditioning card selectively delays the write data valid window of the bus master card to test the limits of the system board.