TEST AND DIAGNOSTIC ARRANGEMENT FOR DIGITAL COMPUTERS

Test and Diagnostic Arrangement for Digital Computers The invention concerns arrangements and methods for error testing and diagnosing processors, which have logic subsystems interconnected by storage elements. In the error test and diagnostic mode the storage elements are connected in the form of shift register for the shift clock controlled application of test data to the processors and for receiving resultant data therefrom. The resultant data is compared to the desired resultant data and, in the case of a mismatch, an error indicator is set to initiate further action. When testing for the correct implementation of operations and operational secondary functions, a signature generator circuit is provided. The generator circuit includes a test accumulator for accumulating the test and resultant data from the storage elements and a test clock generator and counter for controlling the accumulation. A test memory provides test programs consisting of test data, desired result data and a list of the instructions from the processor instruction set which are to be tested. The signature generator circuit is connected to an interface register and/or a system bus of the processor. The stages of the interface register include the shift register formed by the storage elements.