PLANARIZING LAYER FOR SEMICONDUCTOR SUBSTRATES SUCH AS SOLID STATE IMAGERS
PLANARIZING LAYER FOR SEMICONDUCTOR SUBSTRATES SUCH AS SOLID STATE IMAGERS A device is disclosed comprising a non-planar semiconductor substrate and a planarizing layer thereon, the planarizing layer having a maximum thickness that is no greater than about 3.mu. and a planarization factor P?1.0. In...
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Patent |
| Sprache: | eng ; fre |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | PACE, LAUREL J MCCOLGIN, WILLIAM C |
| description | PLANARIZING LAYER FOR SEMICONDUCTOR SUBSTRATES SUCH AS SOLID STATE IMAGERS A device is disclosed comprising a non-planar semiconductor substrate and a planarizing layer thereon, the planarizing layer having a maximum thickness that is no greater than about 3.mu. and a planarization factor P?1.0. In a preferred embodiment, the layer comprises a polymer formed from a liquid monomer coated onto the substrate and thereafter polymerized. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CA1213964A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CA1213964A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CA1213964A3</originalsourceid><addsrcrecordid>eNrjZPAK8HH0cwzyjPL0c1fwcYx0DVJw8w9SCHb19XT293MJdQ4B8UKdgkOCHENcg4FMZw8FRyDt7-PpohAcAhRU8PR1dHcNCuZhYE1LzClO5YXS3Azybq4hzh66qQX58anFBYnJqXmpJfHOjoZGhsaWZiaOxoRVAADX7SzE</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>PLANARIZING LAYER FOR SEMICONDUCTOR SUBSTRATES SUCH AS SOLID STATE IMAGERS</title><source>esp@cenet</source><creator>PACE, LAUREL J ; MCCOLGIN, WILLIAM C</creator><creatorcontrib>PACE, LAUREL J ; MCCOLGIN, WILLIAM C</creatorcontrib><description>PLANARIZING LAYER FOR SEMICONDUCTOR SUBSTRATES SUCH AS SOLID STATE IMAGERS A device is disclosed comprising a non-planar semiconductor substrate and a planarizing layer thereon, the planarizing layer having a maximum thickness that is no greater than about 3.mu. and a planarization factor P?1.0. In a preferred embodiment, the layer comprises a polymer formed from a liquid monomer coated onto the substrate and thereafter polymerized.</description><edition>4</edition><language>eng ; fre</language><subject>BASIC ELECTRIC ELEMENTS ; CABLES ; CONDUCTORS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; INSULATORS ; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING ORDIELECTRIC PROPERTIES ; SEMICONDUCTOR DEVICES</subject><creationdate>1986</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19861112&DB=EPODOC&CC=CA&NR=1213964A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25555,76308</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19861112&DB=EPODOC&CC=CA&NR=1213964A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>PACE, LAUREL J</creatorcontrib><creatorcontrib>MCCOLGIN, WILLIAM C</creatorcontrib><title>PLANARIZING LAYER FOR SEMICONDUCTOR SUBSTRATES SUCH AS SOLID STATE IMAGERS</title><description>PLANARIZING LAYER FOR SEMICONDUCTOR SUBSTRATES SUCH AS SOLID STATE IMAGERS A device is disclosed comprising a non-planar semiconductor substrate and a planarizing layer thereon, the planarizing layer having a maximum thickness that is no greater than about 3.mu. and a planarization factor P?1.0. In a preferred embodiment, the layer comprises a polymer formed from a liquid monomer coated onto the substrate and thereafter polymerized.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CABLES</subject><subject>CONDUCTORS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>INSULATORS</subject><subject>SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING ORDIELECTRIC PROPERTIES</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1986</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZPAK8HH0cwzyjPL0c1fwcYx0DVJw8w9SCHb19XT293MJdQ4B8UKdgkOCHENcg4FMZw8FRyDt7-PpohAcAhRU8PR1dHcNCuZhYE1LzClO5YXS3Azybq4hzh66qQX58anFBYnJqXmpJfHOjoZGhsaWZiaOxoRVAADX7SzE</recordid><startdate>19861112</startdate><enddate>19861112</enddate><creator>PACE, LAUREL J</creator><creator>MCCOLGIN, WILLIAM C</creator><scope>EVB</scope></search><sort><creationdate>19861112</creationdate><title>PLANARIZING LAYER FOR SEMICONDUCTOR SUBSTRATES SUCH AS SOLID STATE IMAGERS</title><author>PACE, LAUREL J ; MCCOLGIN, WILLIAM C</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CA1213964A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre</language><creationdate>1986</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CABLES</topic><topic>CONDUCTORS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>INSULATORS</topic><topic>SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING ORDIELECTRIC PROPERTIES</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>PACE, LAUREL J</creatorcontrib><creatorcontrib>MCCOLGIN, WILLIAM C</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>PACE, LAUREL J</au><au>MCCOLGIN, WILLIAM C</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>PLANARIZING LAYER FOR SEMICONDUCTOR SUBSTRATES SUCH AS SOLID STATE IMAGERS</title><date>1986-11-12</date><risdate>1986</risdate><abstract>PLANARIZING LAYER FOR SEMICONDUCTOR SUBSTRATES SUCH AS SOLID STATE IMAGERS A device is disclosed comprising a non-planar semiconductor substrate and a planarizing layer thereon, the planarizing layer having a maximum thickness that is no greater than about 3.mu. and a planarization factor P?1.0. In a preferred embodiment, the layer comprises a polymer formed from a liquid monomer coated onto the substrate and thereafter polymerized.</abstract><edition>4</edition><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng ; fre |
| recordid | cdi_epo_espacenet_CA1213964A |
| source | esp@cenet |
| subjects | BASIC ELECTRIC ELEMENTS CABLES CONDUCTORS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INSULATORS SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING ORDIELECTRIC PROPERTIES SEMICONDUCTOR DEVICES |
| title | PLANARIZING LAYER FOR SEMICONDUCTOR SUBSTRATES SUCH AS SOLID STATE IMAGERS |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-15T05%3A47%3A53IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=PACE,%20LAUREL%20J&rft.date=1986-11-12&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECA1213964A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |