INTERFACE CHECKING METHOD AND APPARATUS
The invention determines the existence of abnormal circuit conditions in lines of a group of interface lines without using redundant duplex lines. The interface lines are subdivided into a first group, used when the present invention is being used to locate abnormal circuit conditions, and a second...
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Sprache: | eng ; fre |
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Zusammenfassung: | The invention determines the existence of abnormal circuit conditions in lines of a group of interface lines without using redundant duplex lines. The interface lines are subdivided into a first group, used when the present invention is being used to locate abnormal circuit conditions, and a second group, which is not used when the present invention is being used to locate abnormal circuit conditions. Each first group line is connected to a corresponding input terminal of a first exclusive or gate and a second exclusive or gate at an input and output, respectively. The first and second or gates are input to a matching circuit, an output signal therefrom indicating an abnormal circuit condition in the first line group. As a result, since the first group lines are used when the present invention is being used to locate abnormal circuit conditions, each first group line is tested individually for an abnormal circuit condition. However, since lines of the second group are not used when the invention is locating abnormal circuit conditions, lines of the second group are tested, collectively for an abnormal circuit condition. One line of the first group is connected to an input of the second group. The output of the second group is connected to an additional input of the second exclusive or gate. An output signal from the matching circuit indicates the existence of an abnormal circuit condition in at least one line of either one or both of the first and second group of lines. |
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