FOLDED BIT LINE MEMORY WITH ONE DECODER PER PAIR OF SPARE ROWS

FOLDED BIT LINE MEMORY WITH ONE DECODER PER PAIR OF SPARE ROWS A folded bit line configured DRAM, with even and odd rows of memory cells, also includes spare even and odd rows of memory cells which can be substituted for standard rows found to have defective cells or interconnections. Each of the decoders associated with a standard row includes provisions for being disconnected if found to be associated with a defective row. One common spare decoder is associated with one spare even and one spare odd row of memory cells. Each spare decoder is designed normally to be deselected for any address but to be able to assume the address of any disconnected standard row. Disconnection of a standard decoder and substitution of a spare decoder with the appropriate inclusion of fusible links which are selectively opened by laser irradiation. The use of one spare decoder with both an even and odd row serves to reduce the number of needed spare decoders and thus reduces overall chip size.