MOS VOLTAGE DIVIDER

PHA 1042 7 A simple MOS voltage divider uses three enhancement MOS transistors, which includes one load connected to two drivers in parallel. The gate of one driver is connected to the output node, and the other two gates are connected to the supple voltage. The transistors have a common substrate....

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	KOOMEN, JOANNES J.M, SALTERS, ROELOF H.W
Format:	Patent
Sprache:	eng ; fre
Schlagworte:	AMPLIFIERS BASIC ELECTRONIC CIRCUITRY CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTINGELECTRIC POWER CONTROLLING CONVERSION OR DISTRIBUTION OF ELECTRIC POWER ELECTRICITY GENERATION IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS PHYSICS REGULATING RESONATORS SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES SYSTEMS FOR STORING ELECTRIC ENERGY
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

Beschreibung
Zusammenfassung:	PHA 1042 7 A simple MOS voltage divider uses three enhancement MOS transistors, which includes one load connected to two drivers in parallel. The gate of one driver is connected to the output node, and the other two gates are connected to the supple voltage. The transistors have a common substrate. By proper choice of the transistor geometry only, the output node voltage can be made independent of the threshold and temperature variations for output voltages larger than one threshold and smaller than one-half the supply voltage. Moreover, the ratio between the output and supply voltages remains constant.