TWO-DEVICE MEMORY CELL

TWO-DEVICE MEMORY CELL A two-device memory cell for a memory array comprising a single storage capacitor having its terminals respectively coupled to one end of the respective source-drain paths of a pair of field-effect transistors so as to be in series therewith and float between a pair of bit/sense lines of the memory array respectively coupled to the other end of said paths and thereby provide a differential sense signal. Each of the gate electrodes of said pair of field effect transistors is coupled to the word line of said memory array. The differential sense signal obtained from such an arrangement obviates the need for a dummy cell to provide a reference level for detecting the state of the cell.