ZERO DETECTOR

An integrated circuit comprising first and second read-only memories (ROM), an adder circuit and a NOR gate for determining if the content of an input data word has more zeros than ones. The invention is usable in core memories for the purpose of reducing the power requirements of the core memory. Each of the read-only memories provides a set of output data bits which are less in number than the input data word. These output bits are then applied to the adder circuit where it is determined whether the number of zeros is equal to or greater than the number of ones. The output signals from the adder circuit are applied to the NOR gate which provides a signal to the core memory instructing it to convert all zeros to ones, and all ones to zeros, thereby effecting a reduction in the power requirements of the core memory.