CPU/PARALLEL PROCESSOR INTERFACE WITH MICROCODE EXTENSION

CPU/PARALLEL PROCESSOR INTERFACE WITH MICROCODE EXTENSION There is disclosed a data processing system which employs parallel processors (PP's or P-P's) that are interfaced to the CPU, and which derive their control from microinstructions stored in an extension to the CPU microcode structure. This extension forms part of the CPU/PP interface. The P-P's increase speed of operation of the data processing system in which they are employed by operating synchronously and simultaneously with the CPU when called upon by CPU microcode structure to execute particular algorithms.