SYSTEM AND METHOD FOR CONCURRENT AND PIPELINE PROCESSING EMPLOYING A DATA DRIVEN NETWORK

1481392 Data processing BURROUGHS CORP 31 Jan 1975 [28 Feb 1974] 4208/75 Heading G4A A data processing system includes a plurality of interconnected processing units 10 each connected to a respective storage unit 11 containing control operators. Processing units 10 can be dedicated to different operations, e.g. arithmetic, I/O. Instructions making up a program can be assigned to different processing units and are executed in sequence as the relevant data is transferred from one processing unit to another. This allows parallel execution of non-related procedures and pipelining of procedures to be performed on a stream of data passed from one processing unit to another. The system is data driven in that particular instructions of a program are stored in the storage units connected to different processing units, which instructions are called forth when the appropriate data has arrived at that particular processing unit. The function of the conventional main memory is provided by the sum total of the various storage units 11. Each storage unit 11 may be cyclic and may be a disc, delay line, charge coupled device or bubble memory; alternatively it may be a random-access memory formed of cores or integrated circuits. Each instruction and control operator is built up from two-bit characters (,), 0, 1, and is formed within outer brackets and includes inner brackets, the characters outside the inner brackets identifying what the contents of the following inner brackets represent. For example part of each instruction identifies an address in one of the storage units 11, the addressed control operator and the rest of the instruction controlling the processing unit 10 connected to the respective storage unit. For each instruction the opening and closing brackets are counted, a difference in the counted numbers of opening and closing brackets indicating an error which causes a repeat operation. Each processing unit 10 includes an input queue, an output queue, a control unit, a logic unit, and an interface to the respective storage unit 11. The control unit includes a microinstruction read-only memory. A peripheral device may be connected via an adapter 17 to one of the processing units 10 or to an exchange 12 interconnecting the processing units 10. A number of exchanges 12 may be used each connected via an interface 13 having an input queue 15 and an output queue 14 to a second level exchange 16. Further levels of exchanges may be provided.