circuito silenciador de baixa potência
Described herein is a low power squelch circuit which comprises a clock generation unit to generate first and second phases of a clock signal; a sampling unit to sample a differential input signal according to the first and second phases of the clock signal, the sampler to generate a sampled differe...
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| Hauptverfasser: | , |
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| Format: | Patent |
| Sprache: | por |
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| Zusammenfassung: | Described herein is a low power squelch circuit which comprises a clock generation unit to generate first and second phases of a clock signal; a sampling unit to sample a differential input signal according to the first and second phases of the clock signal, the sampler to generate a sampled differential signal; and a differential amplifier to amplify the sampled differential signal. |
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