INSTRUCTION SEQUENCER BRANCH MECHANISM

A special-purpose, microprogrammed digital subsystem sequences through stored lists of microinstruc­tions to produce various control signals. In response to address signals provided by an address generator (32), the microinstructions are accessed in pairs: A primary microinstruction and a branch or target microinstruction. For the most part, only the primary microinstruction is decoded and executed. However, certain of the ones of primary microinstructions are of the type that require a decision to be made, and the microinstruction stream branches to one of two choices depending upon the out­come of the decision. The target microinstruction forms the first microinstruction of one of the available micro­instruction branches, and, if this branch is taken, is executed in parallel with the branch to avoid time penal­ties. An additional aspect of the invention is that the address generator, which provides address signals to a memory that stores the microinstructions, is cap­able of functioning as a timer circuit.