A re-sequencing unit

A resequencing device for a cell switching system node particularly includes: a time stamp generator (TSG), for allocating a time stamp to each cell, a buffer memory (BM), an address memory (FSAM) for storing the address of the first sub-cell of each cell, a link memory (LM), and a circuit (CU) for recovering the address of the buffer memory containing the first sub-cell of a cell. This circuit particularly including: a content-addressable memory, for storing the waiting cell identifiers, each consisting of the identity of a time interval in which the waiting time of the cell expires, and of the identity of at least one output where the cell has to be sent; and a queue memory for each output, in which is written an order number each time that a waiting time expires for at least one cell which has to be sent on this output; each queue memory being of the content-addressable type, and the numbers being sought in increasing order, when this output is available.