PARALLEL CONTROL FOR A PACKET/FAST PACKET SWITCH

A voice/data packet switch with an improved bus architecture is provided. Accordingly, a parallel control architecture for a packet/fast packet switch, according to the invention, is disclosed herein. This invention provides a voice/data packet/fast packet switch bus architecture with parallel bus s...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser:	THOMAS A. FREEBURG, ROY T OGASAWARA, RICHARD E. WHITE
Format:	Patent
Sprache:	eng
Schlagworte:	ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Beschreibung
Zusammenfassung:	A voice/data packet switch with an improved bus architecture is provided. Accordingly, a parallel control architecture for a packet/fast packet switch, according to the invention, is disclosed herein. This invention provides a voice/data packet/fast packet switch bus architecture with parallel bus structures for control (203) and data (201). Moreover, the present invention provides for a synchronization between the control of the devices sending and receiving packets in a voice/data packet switch. It also provides the capability of having multiple packet devices on a common bus sending/receiving packets from one another. It allows packet devices to send as much or as little information by modifying the control memory. The control of the packet devices can be controlled at a very high bit rate such as, for example, 40 Mbps.