DELAY LINE COMPENSATION NETWORK

A timing generator circuit includes a pair of multitap cascaded delay lines of like construction. Each delay line includes a plurality of sections each of which are constructed to provide the same increment of delay at each tap. A capacitive element connects between predetermined taps of the two del...

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Bibliographische Detailangaben
Hauptverfasser:	C.M. NIBBY, R.B. JOHNSON
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRONIC CIRCUITRY CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS PHYSICS RESONATORS
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Beschreibung
Zusammenfassung:	A timing generator circuit includes a pair of multitap cascaded delay lines of like construction. Each delay line includes a plurality of sections each of which are constructed to provide the same increment of delay at each tap. A capacitive element connects between predetermined taps of the two delay lines to form a compensation network including a predetermined section of each delay line. The compensation network which operates to cancel out the effects of any mismatch resulting from connecting the delay lines in series.