Speed cache having separate arbitration for second-level tag and data cache rams

A cache system for use in computer systems has a tag memory (412), a data memory (416), and a cache control unit (401). The tag memory (412) and data memory (416) are provided with separate address lines. The cache control unit (401) has a first arbitration unit (405) for arbitrating access to the t...

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1. Verfasser:	RAJASEKHAR CHERABUDDI
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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