Speed cache having separate arbitration for second-level tag and data cache rams

A cache system for use in computer systems has a tag memory (412), a data memory (416), and a cache control unit (401). The tag memory (412) and data memory (416) are provided with separate address lines. The cache control unit (401) has a first arbitration unit (405) for arbitrating access to the tag memory (412) and a second arbitration unit (406) for arbitrating access to the data memory (416). Providing separate arbitration units (405, 406) for the tag memory (412) and the data memory (416) allows access of the data memory (416) for a following cycle of a multicycle cache-line read while the tag memory (412) is accessed by a snoop controller (402).