MULTI-PROCESSOR COMPUTER SYSTEM

A multi-processor computer system is distributed over error-isolation areas, each of these areas containing a processor element (12, 14, 16 or 18), an encoder (20, 22, 24 or 26), a section (28, 30, 32 or 34) of a memory and an information-reconstruction section (54, 56, 58 or 60) which are connected in this order in a cyclic path. The processor elements work in parallel on the same data-word, which has a certain length. When the result of the processing has to be stored in the memory, each encoder (20, 22, 24 or 26) forms a code-symbol of shorter length, on the basis of the data-word. The set of code-symbols formed on the basis of the data-word forms a code-word with a larger bit length than the data-word mentioned. By means of an error-correcting code at least one erroneous code-symbol in the code-word can be corrected. The code symbols are stored in the respective memory sections (28, 30, 32 or 34). If the data-word concerned has to be further processed, all corresponding code-symbols are fed to all information-reconstruction sections (54, 56, 58 or 60). Peripheral equipment can be connected in the cyclic path, with implementation of distinctive levels of redundancy.