BUFFER CIRCUIT

A buffer circuit for yielding a high output quickly while consuming low power having an input terminal, an output terminal, a pair of power supply rails, a bootstrapping capacitance, an output circuit coupled between the supply rails and having an input connected to one side of the capacitance and an output connected to the output terminal, a delay device coupled to the input terminal and connected to the other side of the capacitance, the delay time provided by the delay device enabling the capacitance to be charged in response to an input signal applied to the input terminal, and switching means responsive to the change in potential at the other side of the capacitance to lift the potential at the one side of the capacitance above that of the supply rails and thereby lift the potential of the output terminal.