Nonvolatile memory with output mode configuration

A nonvolatile memory includes a memory array and a buffer circuit for applying data read from the memory array to external circuitry. A compensation circuit is coupled to the buffer circuit for providing output compensation to the buffer circuit when enabled. The buffer circuit has (1) a first output speed when the compensation circuit is enabled and (2) a second output speed when the compensation circuit is disabled. A configuration circuit is coupled to the compensation circuit for selectively enabling the compensation circuit such that the buffer circuit can be configured between the first and second output speeds. A method of configuring a nonvolatile memory between a first output speed and a second output speed is also described.