TOPCon cell, method for manufacturing the same, and electrical device

The present application relates to a TOPCon cell, a method for manufacturing the same, and an electrical device. The method includes following steps: texturing a front side of an silicon wafer and then preparing a PN junction; forming a tunnel oxide layer, an intrinsic 5 polysilicon layer, a doped polysilicon layer, and a silicon oxide mask layer in sequence on a back side of the silicon wafer, wherein the tunnel oxide layer is deposited by PEALD at a deposition temperature of 150 °C to 200 °C, the doped polysilicon layer is deposited by PECVD, and the silicon oxide mask layer has a thickness of 10 nm to 40 nm; removing a wraparound silicon oxide mask layer material and a wraparound polysilicon layer material 10 from the front side of the silicon wafer, and then removing the silicon oxide mask layer from the back side; and forming a front electrode on the PN junction and a back electrode on the doped polysilicon layer, respectively.