A METHOD FOR FPGA IMPLEMENTATION OF AES ALGORITHM WITH ENHANCED SECURITY FEATURES

Abstract The present disclosure relates toa method for an efficient AES implementation using a FPGA with an enhanced security features. The method comprises: creating a PN sequence generator using a Linear Feedback Shift Register wherein, a number of states generated by the LFSR is determined by a f...

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Hauptverfasser:	Sapkal, Ashok, Zodpe, Harshali
Format:	Patent
Sprache:	eng
Schlagworte:	ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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