A METHOD FOR FPGA IMPLEMENTATION OF AES ALGORITHM WITH ENHANCED SECURITY FEATURES

Abstract The present disclosure relates toa method for an efficient AES implementation using a FPGA with an enhanced security features. The method comprises: creating a PN sequence generator using a Linear Feedback Shift Register wherein, a number of states generated by the LFSR is determined by a feedback taps of a Generator Polynomial wherein, the feedbacks taps comprising a bits are XO Red and a feedback from a MSB side on each clock cycle results in cyclic shifting of previous value; and storing an output states of 8-bit each of the PN Sequence Generator in a Look up Table (LUT) and the output states are given as an input to 256:1 multiplexer wherein, an 8-bit counter generates a value of 8-bit select lines of the multiplexer and wherein, a counter is designed to count 16 states so as to select 16 input bytes and form the 128-bit value at the output. c~S a Cd _ II"~I 44 U - g---~~ .0 LSJ ~' C-. Cd Cd ri a') a KY bO a * Co N _____ :2 N - _____ -