Sensor interposers employing castellated through-vias

An example sensor interposer (100) employing castellated through-vias (118) formed in a PCB (110) includes a planar substrate (110) defining a plurality of castellated through-vias (118); a first electrical contact (114) formed on the planar substrate (110) and electrically coupled to a first castellated through-via (118); a second electrical contact (112) formed on the planar substrate (110) and electrically coupled to a second castellated through-via (118), the second castellated through-via (118) electrically isolated from the first castellated through-via (118); and a guard trace (116) formed on the planar substrate (110), the guard trace (116) having a first portion (116a) formed on a first surface of the planar substrate (110) and electrically coupling a third castellated through-via (118) to a fourth castellated through-via (118), the guard trace (116) having a second portion (116b) formed on a second surface of the planar substrate (110) and electrically coupling the third castellated through-via (118) to the fourth castellated through-via (118), the guard trace (116) formed between the first (114) and second (112) electrical contacts to provide electrical isolation between the first (114) and second (112) electrical contacts.