Method and apparatus for redundant data processing

An arrangement (10) for redundant data processing comprises an integrated circuit (20) in which the functionality of a multi-core processor (30) is implemented. Processor cores (40; 50) of the multi-core processor are each designed to execute a useful program, wherein results which emerge from execution of the useful program by different ones of the processor cores can be compared by means of a comparison module (60) of the arrangement. The processor cores differ from one another with respect to an address or data structure (AS1, AS2; DS1, DS2) which is used by a processor core to respectively store and read data in or from a memory area (70; 80) assigned to the particular processor core. The individual processor cores are at least partially implemented separately in the integrated circuit using hardware.