ON CHIP NETWORK

An OCN for integrated processing elements including a network with multiple ports and multiple port interfaces. The ports and the port interfaces conform to a consistent port protocol. Each port interface converts information between bus transactions of a corresponding processing element and network...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: MARK, W. NAUMANN, NED, D. GARINGER, GARY, A. WALKER, MARTIN, L. DORR
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:An OCN for integrated processing elements including a network with multiple ports and multiple port interfaces. The ports and the port interfaces conform to a consistent port protocol. Each port interface converts information between bus transactions of a corresponding processing element and network packets and exchanges network packets with other port interfaces. Each port includes an arbitration interface and a data interface and the network includes an interconnect and an arbiter. The interconnect includes selectable data paths between the ports for packet datum transfer. A port source interface submits transaction requests and provides packet datums upon receiving an acknowledgement. A port destination interface receives packet datums via available input buffers. Each transaction request includes a transaction size and a destination port address. The arbiter receives transaction requests, arbitrates among transaction requests, provides acknowledgements and controls the interconnect to select data paths between sources and destinations.