LVDS-TREIBER MIT VORVERZERRUNG

A Low Voltage Differential Signaling ÄLVDSÜ Driver with Pre-emphasis and comprising a primary stage (MP3-MP6, MN3-MN6) having a first switching circuit (MP5, MP6, MN5, MN6) arranged to provide a sequence of pulses (OUT1; OUT2) at a predetermined current level (11), a secondary stage (MP7-MP9, MN7-MN9) having a second switching circuit (MP8, MP9, MN8, MN9) arranged to provide an additional current level (I2) for the pulses, and a control circuit arranged to provide control signals (A, A,B, B) for controlling the first and second switching circuits. The control circuit is adapted to detect a difference in level between two consecutive pulses of the sequence and to provide accordingly control signals (A, A,B, B) to the first (MP5, MP6, MN5, MN6) and second (MP8, MP9, MN8, MN9) switching circuits. The control signals are such that when two consecutive pulses of the sequence are different, the additional current level (I2) is added to the predetermined current level (I1), whilst when two consecutive pulses of the sequence are identical, the additional current level (I2) is subtracted from the predetermined current level (I1).