VERFAHREN UND ANORDNUNG ZUR KONTROLLE DER UMWANDLUNG VIRTUELLER ADRESSEN IN PHYSIKALISCHE ADRESSEN IN EINEM COMPUTERSYSTEM

In the field of high speed computers it is common for a central processing unit to reference memory locations via a virtual addressing scheme, rather than by the actual physical memory addresses. In a multi-tasking environment, this virtual addressing scheme reduces the possibility of different programs accessing the same physical memory location. Thus, to maintain computer processing speed, a high speed translation buffer 30 is employed to perform the necessary virtual-to-physical conversions for memory reference instructions. A translation buffer fixup unit 52 is employed to update the translation buffer 30 with the most recently accessed physical memory locations. Therefore, subsequent virtual memory references to these same locations are quickly processed without reference to the much slower main memory 14. The translation buffer fixup unit 52 consists of a state machine 66 controlling hardware specifically designed for the purpose of updating the translation buffer 30. These translation buffer updates are performed immediately after a "miss" is detected by stalling the translation buffer 30 to prevent subsequent conversions until the update is completed.