Realization of a novel fault tolerant reversible full adder circuit in nanotechnology

In parity preserving reversible circuit, the parity of the input vector must match the parity of the output vector. It renders a wide class of circuit faults readily detectable at the circuit’s outputs. Thus reversible logic circuits that are parity preserving will be beneficial to the development of fault tolerant systems in nanotechnology. This paper presents an efficient realization of well-known Toffoli gate using only two parity preserving reversible gates. The minimum number of garbage outputs and constant inputs required to synthesize a fault tolerant reversible full adder circuit has also been given. Finally, this paper presents a novel fault tolerant reversible full adder circuit and demonstrates its superiority with the existing counterparts.