Verification, Validation and Accreditation using AADL

As systems become more software intensive and complex, managing their development and implementation also becomes more complex. Models in development today are isolated, domain-specific artifacts that are created throughout the design lifecycle. A mechanism is needed to integrate the design models with simulation environments as the models are being developed and refined in order to rapidly see the impacts as the design matures. The ability to perform verification, validation, and accreditation (VV&A) early in the modeling process and throughout the lifecycle could greatly improve the model and its contribution. But in order to perform VV&A on complex systems, a precise language would be required to model these systems in an integrated fashion to remove ambiguity and the segmented developmental lifecycle. Objectives of this research included exploring the unique capabilities of Architectural Analysis and Design Language (AADL) for developing high confidence (verified and validated) models as part of a system development lifecycle and to determine the maturity of the AADL tools for VV&A model refinement. This report has two parallel components where the first component is focused on an AADL approach and exploits synergies and the other component is focused on a SYSML based approach. Prepared in cooperation with University of Alabama Huntsville and Georgia Institute of Technology. This Final Technical Report is broken down into two components: University of Alabama Huntsville pages 3 33 and Georgia Institute of Technology pages 34 - 159. The original document contains color images.