Nanosecond Thermal Processing for Self-Aligned Silicon-on-Insulator Technology

Future radar and communications systems will have the need to use CMOS integrated circuits to provide increased analog and digital functions. Conventional CMOS technology has been locked into designing processes around polysilicon gate material because of the need for self-alignment. Low-resistance metal gates are superior for high-speed devices; however, their low melting point prevented their use in a self-aligned structure that experiences high-temperature processing (700 oC). Silicon-on-Insulator (SOI) technology, non-refractory metal gates, and nanosecond laser processing were used to fabricate a self-aligned structure. These techniques will allow further scaling of CMOS devices and enable mixed-mode devices to be integrated on the same substrate. The laser is used to rapidly, on the order of nanoseconds, melt and redistribute the implanted dopants for the source and drain with minimal lateral diffusion, which lowers parasitic gate to drain and source overlap capacitance. Gate resistance can be lowered by at least an order of magnitude and optimal threshold control of pMOS and nMOS devices can be achieved by using an aluminum metal gate instead of a polysilicon gate. This process allows high-performance, low-power digital technology to be integrated with high Fmax, low-noise RF devices. This is a work of the United States Government and therefore is not copyrighted. This work may be copied and disseminated without restriction. Many SSC San Diego public release documents are available in electronic format at http://www.spawar.navy.mil/sti/publications/pubs/index.html, The original document contains color images.