Design, Testing, and Evaluation of GaAsPN Sequence Generator Circuits Implemented in DCFL and TDFL

Spaceborne and military communications hardware demands very high speed circuitry even under high radiation exposure. GaAs field effect transistors have the desirable quality that they possess rapid switching rates and are inherently more resistant to total-dose radiation induced failure than their...

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Bibliographische Detailangaben
1. Verfasser:	Schimpf, Michael W
Format:	Report
Sprache:	eng
Schlagworte:	CARRIER MOBILITY COMMUNICATION EQUIPMENT COMPLEMENTARY METAL OXIDE SEMICONDUCTORS Computer Hardware COMPUTERS DCFL(DIRECTLY COUPLED FET LOGIC) DIGITAL SYSTEMS DIRECTLY COUPLED DYNAMIC LOGIC DYNAMICS Electrical and Electronic Equipment ENERGY CONSUMPTION EXPOSURE(GENERAL) FIELD EFFECT TRANSISTORS GALLIUM ARSENIDES GENERATORS HIGH VELOCITY INTEGRATED CIRCUITS LOGIC Logistics, Military Facilities and Supplies MESFET(METAL SEMICONDUCTOR FIELD EFFECT TRANSISTOR) MILITARY APPLICATIONS MILITARY EQUIPMENT PNSG(PSEUDO-NOISE SEQUENCE GENERATOR) PSEUDO NOISE SYSTEMS RADIATION HARDENING SEQUENCES SILICON SIMULATION SPACEBORNE SPREAD SPECTRUM SWITCHING TDFL(TWO PHASE DYNAMIC FET LOGIC) TEST AND EVALUATION THERMAL CONDUCTIVITY THESES TWO PHASE DYNAMIC FET LOGIC TWO PHASE FLOW
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Beschreibung
Zusammenfassung:	Spaceborne and military communications hardware demands very high speed circuitry even under high radiation exposure. GaAs field effect transistors have the desirable quality that they possess rapid switching rates and are inherently more resistant to total-dose radiation induced failure than their silicon CMOS counterparts. This thesis project involves the design. simulation, submission for fabrication. testing. and evaluation of a 1 -GHz. 7-bit, pseudo-noise sequence generator (PNSG) which has numerous communications applications. particularly in spread-spectrum communications. The basic design of the PNSG is provided first,then topology-specific design considerations are covered for directly-coupled FET logic (DCFL) and two-phase dynamic FET logic (TDFL) implementations. Analysis and comparison of circuit performance characteristics are completed, demonstrating the significant improvement in speed, layout area, and power consumption that dynamic logic offers.