Double-Gate SOI/MOS Devices and Circuits in Hostile Environments

Bulk silicon Complementary-Metal-Oxide-Semiconductor (CMOS) is the dominant market technology in the digital integrated circuit world with two main drivers: memory devices and microprocessors. In the bulk MOS technology, the interaction between the active devices and the semi-infinite substrate results in parasitic effects such as the latchup (the unwanted triggering of parasitic pnpn thyristors formed by CMOS bulk structures in their well) and large parasitic capacitances (inherent to the reverse-biased junctions that isolate the devices from one another). When technology dimensions shrink, latchup becomes a severe problem because the gain of the parasitic bipolar structures becomes large. Also, higher substrate doping concentrations are used, which increases junction capacitances. A solution to these problems is found by isolating the device from the substrate. Since the beginning of the eighties, several techniques have been developed for producing a thin film of single-crystal silicon on top of an insulator 1 In these Silicon-on-Insulator (SOI) technologies, devices are dielectrically isolated from the others. Switching from junction to dielectric isolation suppresses wells and offers tremendous advantages: the latchup and leakage paths between devices are ruled out, the fabrication process is simplified and the integration density is increased. Also, the presence of the insulator layer (generally SiO2) suppresses the well-to-substrate and fringing field capacitances. In addition, the polysilicon- and metal-to-substrate capacitances are limited by the buried insulator capacitance, which is typically lower than the junction capacitance of a bulk MOSFET. For the same reason, the drain/source-to-substrate parasitic capacitances are reduced by a factor 4 to 7 and are much less sensitive to the supply voltage.