Development of the Kalman Filter Application and a VHDL Model for the AFIT (Air Force Institute of Technology) Floating Point Application Specific Processor (FPASP)

The Air Force Institute of Technology (AFIT) is conducting research that will lead to the development of a Floating Point application Specific Processor (FPASP). The FPASP architecture is designed around two independent 32 bit data paths that work in tandem to support full IEEE double precision floating point operations, or that can work independently for 32 bit integer processing. Designed to operate at 25 MHz, the FPASP will be capable of performing 25 million floating point operations per second. A rapid prototyping methodology has been developed for the FPASP. A user identifies an application that could benefit from a VLSI solution. An algorithm of the application is translated into FPASP microcode which can then be programmed into the Laser Programmable Read Only Memory (LPROM) of a blank FPASP. The programmed FPASP can then be mounted on a circuit card and installed in a host system where it would function as a hardware accelerator supporting the user application. In the first part of this thesis, a user application, the Kalman Filter algorithm, is translated into FPASP microcode for programming into the FPASP. In part two, the feasibility of using the VHSIC (Very High Speed Integrated Circuitry) Hardware Design Language Language (VHDL) to model a complete system is demonstrated by developing a register transfer level model of the FPASP. (KR)