A STUDY OF FAILURE MECHANISMS IN SILICON PLANAR EPITAXIAL TRANSISTORS

Initial reverse currents in gold-doped devices such as the FT1312 npn transistor are due primarily to generation levels associated with gold within the depletion region of the metallurgical junction. At 20 volts reverse bias, small increases in the reverse current are seen. Beyond this threshold voltage only an order of magnitude of increase in reverse current occurs. The time required to reach this saturation level of reverse current is consistent with this transistor geometry and with the times seen in the high temperature reverse bias (HTRB) test matrix. Completion of the 2000-hour stress test showed that very high stress for a long period of time was required to create failures, 95% of which were metal opens. The large majority of these failures occurred on HTRB at 80v and 250 C, a condition which maintained the units in continuous avalanche breakdown as well as high temperature. The stresses generated in the silicon lattice due to emitter impurity diffusion were responsible for abnormal base diffusion, termed the Cooperative Diffusion Effect.