High performance ACS for Viterbi decoder using pipeline T-Algorithm

Viterbi algorithm is the most popular algorithm used to decode the convolution code, but its computational complexity increases exponentially with the increasing constraint length due to the large number of Trellis transitions. However, high constraint length is necessary to improve the accuracy of the decoding process for the high rate convolution code. In particular, the Add Compare Select (ACS) module of the Viterbi Decoder will have large numbers of trellis states and trellis transitions with increased constraint lengths, which give rise to high hardware complexity and large power consumption. As the performance of Viterbi decoder mainly depends on its efficient implementation of ACS module, in this paper, we propose a modified pipelined architecture for the ACS of Viterbi decoder. This is derived by employing the technique of re-timing; further the architecture is also reconfigured to support various wireless standards. The architecture has been implemented in Xilinx Vertex 6 FPGA device to make the comparison between our architecture and the existing architecture. From the analysis done on ACS implementation, it is found that the resource requirements, delay and power consumption are optimized significantly for the proposed architecture compared to existing pipelined architecture. The results obtained from the analysis show that frequency of the system is increased up to 165MHz with reduced area. The cell level performance is also obtained using Cadence Encounter (R) tool with TSMC 180nm CMOS technology.