EMPLOYING COMPLEXITY ESTIMATES OF BINARY DECISION DIAGRAMS IN THE SYNTHESIS OF LOGICAL CIRCUITS

EMPLOYING COMPLEXITY ESTIMATES OF BINARY DECISION DIAGRAMS IN THE SYNTHESIS OF LOGICAL CIRCUITS

A formula is suggested to evaluate the area of a logical circuit that is built in a given library of logical elements according to the BDD (Binary Decision Diagram) representation of a system of Boolean functions. The experimental results of synthesis of combinational logical circuits from the minim...

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Veröffentlicht in:Informatika (Minsk, Belarus) Belarus), 2016-09 (2), p.85-93
Hauptverfasser: N. A. Avdeev, P. N. Bibilo
Format: Artikel
Sprache:rus
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Zusammenfassung:A formula is suggested to evaluate the area of a logical circuit that is built in a given library of logical elements according to the BDD (Binary Decision Diagram) representation of a system of Boolean functions. The experimental results of synthesis of combinational logical circuits from the minimized BDD representations in the design library of custom CMOS VLSI circuits are described.
ISSN:1816-0301