A four‐stage yield optimization technique for analog integrated circuits using optimal computing budget allocation and evolutionary algorithms

A high yield estimation is necessary for designing analogue integrated circuits. In the Monte‐Carlo (MC) method, many transistor‐level simulations should be performed to obtain the desired result. Therefore, some methods are needed to be combined with MC simulations to reach high yield with high speed at the same time. In this paper, a four‐stage yield optimisation approach is presented, which employs computational intelligence to accelerate yield estimation without losing accuracy. Firstly, the designs that met the desired characteristics are provided using critical analysis (CA). The aim of utilising CA is to avoid unnecessary MC simulations repeating for non‐critical solutions. Then in the second and third stages, the shuffled frog‐leaping algorithm and the Non‐dominated Sorting Genetic Algorithm‐III are proposed to improve the performance. Finally, MC simulations are performed to present the final result. The yield value obtained from the simulation results for two‐stage class‐AB Operational Transconductance Amplifer (OTA) in 180 nm Complementary Metal‐Oxide‐Semiconductor (CMOS) technology is 99.85%. The proposed method has less computational effort and high accuracy than the MC‐based approaches. Another advantage of using CA is that the initial population of multi‐objective optimisation algorithms will no longer be random. Simulation results prove the efficiency of the proposed technique. A high yield estimation is necessary for designing analog integrated circuits (IC). In this paper, a four‐stage approach is presented that is employed computational intelligence to accelerate up yield estimation without losing accuracy.