Strained Silicon Single Nanowire Gate-All-Around TFETs with Optimized Tunneling Junctions

The main constraint of metal-oxide-semiconductor field-effect transistor (MOSFET) for addressing these issues is the inverse subthreshold swing SS (= dVg/dlog(Id) ), which is limited to 60 mV/dec at room temperature. [...]any attempt to scale Vdd by adjusting threshold voltage Vth will lead to exponentially higher Ioff-current, deteriorating the switching ratio. [...]to the other materials, silicon-based TFETs generally show better performance in terms of minimum SS and switching ratio, mainly due to the maturity of silicon fabrication technology. [...]silicon TFETs are compatible with the conventional CMOS fabrication process, which keeps the costs low and makes it feasible to realize complementary TFET circuits [6,7]. A TFET works in both modes, p- and n-type, due to the presence of tunneling junctions at both the source and drain side, which causes undesired ambipolar switching, a typical behavior of a TFET. [...]the p-TFET shows higher on current Ion than n-TFET, corresponding to an Ion of 2.41 µA/µm for p-TFET and 0.78 µA/µm for n-TFET respectively, at Vds = Von = Vg − Voff = −0.5 V for an Ioff = 1 nA/µm. The reason that n-TFETs show lower current could be due to the broader tunneling junction caused by faster B diffusion. The latter is a key performance parameter for analog applications, for example, a current mirror. [...]the on current was also improved compared to the Set 2 devices, showing Ion = 15 µA/µm at Vov = Vgs − Voff = 0.5 V with an Ioff = 1 nA/µm. The average SS was also improved to 76 mV/dec over 4 orders of drain current Id.