A FPGA-based Configurable Chassis Parallel Bus Technology

In some existing application scenarios, industrial control platforms have expandable requirements for the data space management of chassis parallel bus. In this paper, a new chassis parallel bus technology scheme that can be flexibly configured and efficiently expanded is proposed. By separating the configuration space from the existing bus address space, the function partition of the configuration space is used to realize the functions of device plug identification, data space dynamic allocation, emergency broadcast, port data transmission, etc. At the same time, the hardware environment of multiple plug-in chassis based on parallel bus is built, and the functional test and verification of the technical scheme are carried out by using plug-ins with field programmable gate array (FPGA) devices. The test results show that all functions are normal, indicating that the parallel bus technology completely achieve the functional design goal based on FPGA. In addition, the bus scheme has completed a half-year operat