A Device Independent High Grade Implementation of AESon Xilinx FPGA'S

The paper proposes a way for the implementation the Advanced Encryption Standard (AES), by matching the algorithm requirements with the hardware (specifically the Xilinx FPGA's) requirements. The aim from the new proposal was an implementation that is not restricted to a particular device. Instead a one guided by the customer requirements, that’s to say transforming the AES architecture to general purpose tool. Finally, a comparison of the proposed implementation with other implementation of the AES using FPGA was made and assessed. The results clearly demonstrate the efficiency of the proposed implementation.