Tapered Cross Section Photoelectron Spectroscopy Provides Insights into the Buried Interfaces of III‐V Semiconductor Devices

Interfaces are key elements that define electronic properties of the final device. Inevitably, most of the active interfaces of III–V semiconductor devices are buried and it is therefore not straightforward to characterize them. The Tapered Cross Section Photoelectron Spectroscopy (TCS‐PES) approach is promising to address such a challenge. That the TCS‐PES can be used to study the relevant heterojunction in epitaxial III–V architectures prepared by metalorganic chemical vapor deposition is demonstrated here. A MULTIPREP polishing system that enables controlling the angle between the sample holder and the polishing plate has been employed to improve the reproducibility of the polishing procedure. With this procedure, that preparing the TCS of III–V semiconductor devices with tapering angles lower than 0.02° is possible is demonstrated. The PES provides then information about the buried interfaces of Ge|GaInP and GaAs|GaInP layer stacks. Both, chemical and electronic properties have been measured by PES. It evidences that the preparation of the TCSs under an uncontrolled atmosphere modifies the pristine properties of the critical buried heterointerfaces. Surface states and reaction layers are created on the TCS surface, which restrict unambiguous conclusions on buried interface energetics. Tapered Cross Section Photoelectron Spectroscopy (TCS‐PES), a promising method to investigate the chemistry and electronic structure at buried interfaces in semiconductor devices, is for the first time used on III–V architectures. PES yielded insight into the chemistry at the buried interfaces, but polishing induced alterations limit the information on interface energetics.