Mitigation of Insulator Lightning-Induced Voltages by Installing Parallel Low-Voltage Surge Arresters

In this paper, we propose a mitigation method for reducing lightning-induced insulator voltages based on the installation of low-voltage surge arresters aligned parallelly to the insulator. The three-dimensional finite-difference time-domain (FDTD) method is applied to numerically model a real surge arrester residual voltage evaluation system. The application of a transient current pulse, typical of lightning discharges, is considered in our numerical model. We considered cases with one or two surge arresters installed per phase, in three different geometric and parametric configurations for installing distribution surge arresters. In addition to the Kirchhoff current division, which reduces both the absorbed energy and the thermal stress, the results associated with the installation of two surge arresters parallelly aligned to the insulator show that the interaction of magnetic fields generated by the surge arresters’ currents can produce an additional strong reduction in lightning-induced voltage over the insulator, as presented in this paper. Conditions for maximum voltage reduction are also identified. A brief cost-effectiveness analysis is also provided.