Characterization of top barrier thickness from gate capacitance of high mobility III-V semiconductor MOS-HEMT devices

We investigate the effect of varying the top barrier thickness on the gate C–V characteristics of InGaAs and InSb MOS-HEMT devices. The gate capacitance of these devices exhibits a sharp increase at certain gate voltages under both accumulation and inversion bias. The gate voltages at which some of these sharp changes occur depend on the thickness of the top barrier layer. The sharp rise in gate capacitance appears as a peak in the derivative of the capacitance with respect to the gate voltage. The positions of certain peaks of the derivative as a function of the gate voltage give information on the thickness of the top barrier layer. By exploiting this trend it is possible to extract the barrier thickness from the gate C–V characteristics.