12b 500MS/s successive‐approximation‐register‐assisted pipeline analogue‐to‐digital convertor using a four‐stage ring amplifier with coarse‐analogue‐to‐digital convertor embedded

This article presents a 12b 500MS/s successive‐approximation‐register‐assisted pipeline analogue‐to‐digital converter. By adopting a new auto‐zero scheme, a calibration‐free four‐stage ring residue amplifier with a small offset cancellation capacitor is proposed. In addition, the coarse‐analogue‐to‐digital converter of the second stage is embedded into the amplification phase, which relaxes the comparison periods of the first and second stages by 25.0% and 17.4%, respectively. Post‐simulated in 28‐nm CMOS technology with a 0.9 V supply, the analogue‐to‐digital converter achieves 62.2 dB SNDR and 78.1 dB SFDR. It consumes 8.45 mW with an on‐chip reference voltage buffer, resulting in Schreier's figure of merit (FoMS) of 166.9 dB. This article introduces a new scheme to fulfil four‐stage ringamp as a potential choice to reach both high gain and high speed. Besides, the coarse‐ADC‐embedded structure allows 3‐b comparison without occupying the timing of the next pipeline stage. These two techniques are adopted in the proposed pipelined ADC and push the power and area efficiency for high performance.