Design and implementation of high speed serial interface controller circuit for 3 GS/s 12 bit ADCs

High performance data converter is the core device of the fifth generation mobile communication base station system. Its sampling rate is no less than 3 GS/s and the resolution is higher than 12 bit. Therefore, it is inevitable for high-speed serial interface to replace traditional interface circuits. Based on JESD204B protocol, this paper designs a high speed serial interface control layer circuit applied to 3 GS/s 12 bit ADCs. Under the premise of ensuring high-speed transmission, it considers the power consumption and resources in the compromise. The circuit adopts the pre-frequency technique to complete the framing in the transmission layer, and the 8 B/10 B coding is implemented by using the polar information to simplify encoding techniques in the data link layer. In Vivado 16.1 environment, using the Xilinx ZC706 FPGA PHY IP and JESD204B Receiver IP, the verification of the interface circuit proposed in this paper is completed. The experimental results show that the data transmission is correct, the ser