Real-Time Implementation of a New Modified 3DSVPWM Control Method for Eliminating Zero-Sequence Circulating Current in Parallel Three-Phase Four-Leg Source Voltage Inverters

Due to its good reliability, high modularity, zero-sequence current (ZSC) path, and lower size and cost, the parallel four-leg source voltage inverter's topology is a perfect choice for many power applications, including renewable power generation-based stand-alone power-supply systems (SAPSSs). However, the major concern associated with this topology is the presence of a zero-sequence circulating current (ZSCC) that circulates between the phase legs of these inverters when the inverters operate under unbalanced current sharing or unbalanced output-filter parameters, which leads to multiple consequences, including output current distortion, power losses, and system stability degradation, as well as impacting the efficiency, reliability, and operational lifespan of the system. The ZSCC model demonstrates that the ZSCC amplitude is linked to the filter inductance and difference between zero-sequence duty ratios or zero-sequence voltages (ZSVs). Considering these facts, we propose a new modified three-dimensional space vector pulse width modulation (3DSVPWM) methodology to suppress ZSCC and its effects on the current quality, efficiency, reliability, and operational lifespan of the parallel system. The suggested strategy aims to eliminate the difference between ZSVs by adjusting the zero-vector duty ratios in each switching period. This adjustment keeps the ZSCC constant at zero with minimal oscillations and switching losses, thereby improving the output current quality, particularly in mitigating the 3^{\mathrm {rd}} harmonic and its multiples, and enhancing the system's efficiency, reliability, and operational lifespan. The proposed method offers the advantages of being suitable for suppressing both the ZSCC and ZSC and not impacting the control purposes or the system's output quality. The efficiency and performance of the designed method are validated through various Hardware-in-the-loop (HIL) tests under different conditions using the OPAL-RT-OP5700 real-time simulator.