Design and Analysis of a Multirate 5-bit High-Order 52 fsrms Δ ∑ Time-to-Digital Converter Implemented on 40 nm Altera Stratix IV FPGA

This paper describes FPGA implementation of a high-order continuous-time multi-stage noise-shaping (MASH) \Delta \Sigma time-to-digital converter (TDC). The TDC is based on Gated Switched-Ring Oscillator (GSRO) and employs multirating technique to achieve improved performance over conventional \Delta \Sigma TDCs. The proposed TDC has been implemented on an Altera Stratix IV FPGA development board. Dynamic and static tests were performed on the proposed design and experimental results demonstrate that it can perform its function without the need of calibration. The built-in clock circuitries of the FPGA board provides sampling clocks and operating frequencies of the GSROs. This work presents a 52 fs rms , 89.7 dB dynamic range and 0.18 ps time-resolution at 200 MHz, 800 MHz, 1600 MHz sampling rate at the first, second and third stage, respectively, which demonstrate that the proposed third-order TDC can play an important role in applications such as ADPLLs and range finders in which accuracy and speed are vital.