Improved Decoding Algorithms for Convolutional Codes

Introduction. The considered implementation of the Viterbi algorithm provides a reduction in hardware and time costs for decoding convoluted code sequences, and can be used for semi-realistic modeling of existing means of data transmission (for example, in satellite communication). The purpose of the article. Show how when modeling the processes of encoding and decoding convolutional codes according to the improved Viterbi algorithm, as well as its implementation based on programmable logic devices of the FPGA type, it was possible to reduce the number of clocks of reading metrics and tracks from RAM by 2 times. The results. A two-fold decrease in the number of reading cycles of metrics and tracks (input sequences or reverse pointers) from RAM is achieved by joint processing of two receiver nodes that share two source nodes. Relatively small costs for a hardware calculator of edge metrics allow you to organize parallel calculation, comparison and multiplexing of metrics and tracks of two sources at the inputs of block RAM. Two-port block memory makes it possible to significantly (up to two times) speed up the decoding process, to abandon metric and track buffer registers. Conclusions: The Viterbi decoder is widely used in communication systems and is a practical method of error correction at high signal transmission speed in modern telecommunication systems. The Viterbi decoder is designed for decoding convolutional codes and is optimal in the sense of minimizing the probability of an error. The advantage of the Viterbi decoder is that its complexity is a linear function of the number of symbols in the codeword sequence. In addition, the Viterbi algorithm is widely used in pattern recognition systems using hidden Markov models. Keywords: Convolutional codes, Viterbi algorithm, FPGA basis, metrics.