Monolithic 3D integration of 2D transistors and vertical RRAMs in 1T–4R structure for high-density memory

Emerging data-intensive computation has driven the advanced packaging and vertical stacking of integrated circuits, for minimized latency and energy consumption. Yet a monolithic three-dimensional (3D) integrated structure with interleaved logic and high-density memory layers has been difficult to achieve due to challenges in managing the thermal budget. Here we experimentally demonstrate a monolithic 3D integration of atomically-thin molybdenum disulfide (MoS 2 ) transistors and 3D vertical resistive random-access memories (VRRAMs), with the MoS 2 transistors stacked between the bottom-plane and top-plane VRRAMs. The whole fabrication process is integration-friendly (below 300 °C), and the measurement results confirm that the top-plane fabrication does not affect the bottom-plane devices. The MoS 2 transistor can drive each layer of VRRAM into four resistance states. Circuit-level modeling of the monolithic 3D structure demonstrates smaller area, faster data transfer, and lower energy consumption than a planar memory. Such platform holds a high potential for energy-efficient 3D on-chip memory systems. Designing a monolithic 3D structure with interleaved logic and high-density memory layers has been difficult to achieve due to challenges in managing the thermal budget. Here, the authors demonstrate a 3D integration of monolayer MoS 2 transistors with 3D vertical RRAMs through a low-temperature fabrication process whose 1T– n R structure shows high promise for low-power and high-density memory applications.